1. Field of the Invention
The present invention relates to a signal processor and method for processing a signal, capable of executing an encoding and a decoding of the signal.
2. Description of the Related Art
A signal processor capable of encoding and decoding a video input signal, an audio input signal, and an input bit stream in accordance with a moving picture expert group (MPEG) standard executes the encoding and the decoding by utilizing a reference clock which is a synchronization reference. In decoding the input bit stream conformed to MPEG2-transport stream (TS) standard, the reference clock is generated by utilizing a program clock reference (PCR) included in the input bit stream.
On the other hand, in encoding the video input signal and the audio input signal, the reference clock is generated by utilizing one of a video input clock and an audio input clock provided with one of the video input signal and the audio input signal. In this case, phase locked loop (PLL) circuits are required for the video input clock and the audio input clock.
However, since a PLL circuit includes a capacitor having a large capacity, it is difficult to reduce the size of the PLL circuit. Furthermore, PLL circuit costs more than the other digital circuits. Therefore, the cost and the size of the entire signal processor increase in proportion to the number of PLL circuits.